The present invention relates to a charge coupled device (hereinafter, referred to as CCD), and more particularly to a pseudo bi-phase CCD that is capable of improving transmission efficiency by using narrow channel effect.
CCD is one of those broadly called a charge transfer device and is a dynamic element wherein charges move through a specific path according to a control of clock pulse. Due to such characteristics, being coupled with photo diode, the CCD is diversely and widely used in a technology field of making image signal by sensing photo signal. For example, the CCD is used in an image sensor, video camera, facsimile, video signal processing circuit.
A basic structure of the CCD was initially proposed by Boyle and Smith of the Bell Laboratory in 1969. The earliest structure of CCD is formed metal electrodes having arrays of MOS capacitor. The simple lateral arrangement of gate electrodes, however, was found not appropriate in coupling electric potential well, a structure of coupling gates over gates was therefore proposed.
The most well-known structure of these days is a structure wherein gate electrode is formed of poly-crystal silicon which is isolated by oxide film and therebelow insulator and semiconductor areas. The CCD having such structures is called buried type CCD because a channel potential formed below the gate electrode is transferred to the body of the semiconductor.
In the CCD, transmission efficiency is the key to reliability of the element. And in the channel-buried type CCD, transmission efficiency is improved by injecting into a substrate wafer ion impurities which has conductivity type to that of the substrate wafer, or by forming epitaxial layer which has conductivity type opposed to that of the substrate wafer, so as to transfer the charges.
FIG. 1 illustrates pseudo bi-phase CCD structure of prior art that uses such method that sets the channel potential by differentiating thicknesses of gate insulation films. In the cross-section view of FIG. 1, a semiconductor layer (or an epitaxial layer) 11 having a conductivity type opposed to that of a substrate wafer 10 is formed on the substrate wafer 10. Gate electrodes 12-17 having gate insulation films 18, 19 of thicknesses T1, T2 different from each other are formed on the semiconductor layer 11. As for thickness values of the insulation films, T1 is generally 200-500 .ANG. and T2 is 700-1000 .ANG..
The first and second transmission clocks .phi.1, .phi.2 are alternatively applied commonly to the gate electrodes 12, 14 and 16 formed on the gate insulation film 18 of T1 thickness and the gate electrodes 13, 15 and 17 formed on the gate insulation films 19 of T2 thickness. The first and second transmission clocks .phi.1, .phi.2 are signals that have mutually opposing phases as shown in FIG. 2 and first gate voltages VG1 and VG2 are taken as "low" and "high" states respectively.
Accordingly, when a state of the first transmission clock .phi.1 is "high", potential wells 20-23 having well heights of H1, H2, H3 and H4 respectively are formed below the gate electrodes 12-15. Here, it has to be understood that the well heights of H1, H2, H3 and H4 are increased in a direction toward which potential is increased. That is, although the first transmission clock .phi.1 is applied to both the gate electrodes 12 and 13, since the gate insulation film 19 below the gate electrode 13 has thickness T2 that is greater than the thickness T1 of the gate insulation film 18 that is below the gate electrode 12, the potential well 21 formed below the gate electrode 13 also becomes deeper than the potential well 20 formed below the gate electrode 12. And it is the same in the case of the gate electrodes 14 and 15. In this case, an electric charge 26 being transmitted stays in the potential well 23 that has the greatest potential. Here, what is meant by great potential is that the potential well is too high for the electric charge therein to escape.
The charge 26 being transmitted to the right-hand side of the drawing as the first and second transmission clocks .phi.1, .phi.2 are applied to periodically with the phases different from each other as stated above.
Unlike FIG. 1, FIG. 3 illustrates another pseudo bi-phase CCD structure of prior art wherein potential difference is formed by injecting a predetermined ion impurities into a semiconductor layer that is below gate electrodes.
In the structure shown in FIG. 3, ion-injected areas 29, 30 and 31 are formed below every other gate by injecting into a semiconductor layer 28 formed on a substrate wafer 27, ion impurities that have conductivity type opposed to that of the semiconductor layer 28. Gate electrodes 32-37 have gate insulation films that have all the same thickness T3, and neighboring gate electrodes are overlapped. Thereby, the gate electrodes 33, 35 and 37 which have ion-injected areas 29, 30 and 31 therebelow can have greater potential 38, 39 and 40 than the other gate electrodes 32, 34 and 36 to which an identical transmission clock is applied. In the same method as FIG. 1, charge 41 being transmitted stays in the potential well 39 that is the deepest.
Dose density of the ion-injected areas 29, 30 and 31 is approximately 4.0.times.10.sup.11 ions/cm.sup.2 of P-type impurities, when dose density of the semiconductor layer 28 is approximately 3.0.times.10.sup.12 ions/cm.sup.2 of N-type impurities.
As stated above, in the pseudo bi-phase CCD structures of the prior art, the depth of the potential well can be adjusted according to a desired depth, however, since a total of four gate electrodes are required for one transmission stage, it is not only a disadvantage in designing for high-integration but also a blocking element in processing.